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Title of Thesis

Low power and Area Efficient Architecture Design for Moderate Rate Digital systems

Author(s)

Sheikh Muhammad Farhan

Institute/University/Department Details
Department of Electrical Engineering / University of Engineering and Technology, Taxila
Session
2011
Subject
Reconfigureable Computing Plattform
Number of Pages
169
Keywords (Extracted from title, table of contents and abstract of thesis)
Semiconductor, Systems, Technology, Power, Efficiently, Area, Architecture, Digital, Hardware, Algorithms, Low, Domains, Moderate, Machines, Rate

Abstract
Recent advancements in semiconductor technology have sparked a struggle among researchers and manufacturers to best utilize the modern technology trends in designing state of the art digital systems.Devices with small form factors, offering high throughput and low power consumption are very much in demand.These factors have actuated active research in the field of area efficient, low power high speed digital system design.This research is an effort to contribute in this active research area by adding a new dimension to digital design methodology.In addition to this, the research also makes use of established digital design methodologies augmented with the research studies outcome to produce novel designs around few exemplary applications.
The prime focus of this study is to explore Trace Scheduling Methodology and extracts novel algorithm-to-hardware mapping features for efficient hardware design. Trace scheduling is a topic under compiler design theory and is efficiently used to design compliers for VLIW machines.The research, inspired by trace scheduling, introduces the concept of efficient hardware design through identification of traces in the algorithm and their mapping for optimal hardware affinity.The research work first investigates this concept on a relatively simpler design such as an FIR filter in order to establish a link between the two technology domains which are compiler theory and digital system design. Later, the devised methodology is applied on applications from machine vision and cryptography to design area efficient, low power, moderate data rate architectures.The research presents novel hardware mapping of Peak Sorter and Advanced
Encryption Standard (AES) algorithm for moderately high data rate applications.The designs offer a best area performance tradeoff.The utility of the technique developed in this research can be found in mapping complex algorithms in Very Large Scale Integrated (VLSI) circuits and digital design compilers.

Download Full Thesis
2,672 KB
S. No. Chapter Title of the Chapters Page Size (KB)
1 0 CONTENTS

 

 
101 KB
2

1

INTRODUCTION

1.1 Motivation
1.2 Thesis Outline
1.3 References

1
166 KB
3 2 ARCHITECTURAL OPTIONS VS. DESIGN OBJECTIVES

2.1 The Three Words Paradigm
2.2 Design for Speed
2.3 Design for Area
2.4 Design for Power
2.5 References

8
454 KB
4 3 TRACE SCHEDULING- A NEW DIMENSION

3.1 Introduction
3.2 Trace Scheduling
3.3 Convergence of Trace Scheduling
3.4 Trace Scheduling in VLIW Architecture
3.5 Summary
3.6 References

46
287 KB
5 4 TRACE SCHEDULING MODELING FOR HARDWARE AFFINITY

4.1 Hardware Trace Schedule Map for Finite Impulse Response Systems
4.2 Summary

64
391 KB
6 5 TRACE SCHEDULING BASED OPTIMIZATION OF NAVIGATION SYSTEM COMPONENT

5.1 TERCOM
5.2 DSMAC
5.3 High Speed Correlation Sorter
5.4 Peak Sorter in TERCOM and DSMAC
5.5 Hardware mapping of Peak Sorter
5.6 Summary
5.7 References

79
1,177 KB
7 6 TRACE SCHEDULING BASED ADVANCED ENCRYPTION STANDARD (AES)

6.1 Introduction
6.2 Introduction to AES
6.3 Related Work
6.4 AES]8 Architecture
6.5 Summary
6.6 References

108
509 KB
8 7 RESULTS AND ANALYSIS

 

140
282 KB
9 8 CONCLUSION

 

146
111 KB
10

9

APPENDIX

 

150
155 KB