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Title of Thesis

PAPR Reduction in OFDM System

Author(s)

Seema Khalid

Institute/University/Department Details
Department Of Electrical And Computer Engineering, Centre For Advanced Studies In Engineering / University Of Engineering And Technology, Taxila
Session
2010
Subject
Communication / Digital Signal Processing
Number of Pages
105
Keywords (Extracted from title, table of contents and abstract of thesis)
Computational, System, Solution, Deficiencies, Reduction, Architectures, Capacity, Prototype, Programmable, Minimal, Constrain

Abstract
One of the major drawbacks of OFDM has been the high peak-to-average power ratio (PAPR) that is characteristic of signals with multiple sub-carriers.The
high PAPR requires additional back off to achieve linear amplification at the transmitter end which results in inefficient power consumption.This inefficient power consumption is the major impediment in implementing OFDM in portable device. Previous efforts to address this problem have been principally directed at two areas, the reduction of signal PAPR and various methods of achieving linear and efficient power amplification (PA).However, all approaches suffer due to various deficiencies such as complexity, computational time, memory requirements,data rate loss and high distortion.Therefore, this thesis aimed at finding the solution of power control problem by reducing the PAPR of the signal. Two novel techniques are proposed in this thesis. One of the techniques is based on distortion class named as Zero Forcing Peaks (ZFP) and the other is based on Selected Mapping (SLM) technique fromprobabilistic class. In this thesis a new concept of using Learning Vector Quantization (LVQ) along with SLM has been introduced which is named as LVQ-SLM and can be considered as a major contribution of this thesis. Further two different architectures are proposed for LVQ-SLM and their practicability is investigated by synthesizing these architectures on Field Programmable Gate Arrays FPGA.
Result obtained using second technique is quite encouraging. An efficient implementation of SLM is achieved by using LVQ network as it reduces PAPR with minimal computational complexity. The only constrain which has been noted when the number of sub carriers and modulation order increase, the on-chip memory to store prototype vectors and computational requirements also increase.High capacity low power Content addressable memory (CAMs) based hardware can be used to solve this constrain which has also been proposed in this thesis.

Download Full Thesis
643 KB
S. No. Chapter Title of the Chapters Page Size (KB)
1 0 CONTENTS

 

 
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2

1

INTRODUCTION

1.1 Effects Of High Papr
1.2 The Proposed Approach
1.3 The Proposed Algorithm Of Lvq-slm
1.4 Contribution To The Literature
1.5 Organization Of Thesis

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3 2 FUNDAMENTALS OF THE PEAK-TO-AVERAGE POWER RATIO

2.1 Background
2.2 Ofdm System
2.3 Mathematical Model Of Ofdm System
2.4 Cause Of Large Envelop Variations
2.5 Envelope Variation Metrics
2.6 Papr As Metric Of Envelope Variation
2.7 Factors Effecting Papr

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4 3 LITERATURE REVIEW

3.1 Classification Of Existing Techniques
3.2 Reduction Techniques
3.3 Comparison Of Papr Reduction Techniques
3.4 Essential Features In Papr Reduction Technique

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5 4 THE PROPOSED ZERO FORCING PEAKS TECHNIQUE51

4.1 Proposed Model For Zero Forcing Peaks
4.2 Results And Discusions
4.3 Concluding Remarks

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6 5 THE PROPOSED LEARNING VECTOR QUANTIZATION – SELECTED MAPPING TECHNIQUE

5.1 The Usefulness Of Detecting Of High Papr Symbols
5.2 Memory Based Pattern Recognizer
5.3 The Proposed Lvq-slm Technique
5.4 Parameters Of Proposed Lvq.
5.5 Proposed Model And Architecture
5.6 Simulation Results
5.7 Analysis Of The Results
5.8 Concluding Remarks

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7 6 THE PROPOSED FMPP BASED ARCHITECTURE FOR LVQ-SLM

6.1 Motivation For The Fmpp Based Architecture
6.2 Hardware Approach For Lvq-slm
6.3 Fmpp Based Architecture
6.4 Basic Features Of Fmpp
6.5 Remuneration Of Fmpp
6.6 Fmpp Used In Nns
6.7 Proposed Architecture
6.8 Implementation Details
6.9 Concluding Remarks

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8 7 THE PROPOSED CAM BASED ARCHITECTURE FOR LVQ-SLM

7.1 Motivation For The Cam Based Architecture
7.2 Hardware Implementation Of Lvq Classifier
7.3 Proposed Cam Based Architecture
7.4 Results And Discussions
7.5 Concluding Remarks

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9 8 CONCLUSION AND FUTURE WORK

8.1 Conclusion
8.2 Future Work
8.3 Publications

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10 9 APPENDIX AND REFERENCES

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