

Title of Thesis
Efficent Architectural Transformation of Multirate Recursive
Filters. 
Author(s)
Umar Farooq 
Institute/University/Department
Details Department Of Electrical Engineering /
University Of Engineering And Technology, Taxila 
Session 2008 
Subject Engineering Electrical 
Number of Pages 138 
Keywords (Extracted from title, table of contents and
abstract of thesis) Multirate, Architectures, Delay,
Transformation, Differentiators, Multiplies, Rate, Filters,
Successive, Efficent, Recursive, Digital 
Abstract Computationally
efficient architectures of multirate recursive filters are presented
in this thesis. An analytical transformation is introduced that
converts an IIR filter into an efficient decimation/interpolation
filter. The transformation is named as merged delay transformation.
This transformation is applicable to first order and second order
recursive difference equations. The transfer function of the
transformed filter is expressed in the form of H(zM) so that noble
identity of multirate signal processing may be invoked. An Nth order
filter is required to be implemented in parallel using first order
and second order sections.In case of decimation, a down sampler
follows an antialiasing filter. With the help of merged delay
transformation, the filter is transformed and arranged to provide
filtering and down sampling in the same stage. This is possible if
the filter is implemented in parallel form. Architecture is
introduced where down samplers and delays are arranged on the input
side. A commutator switch model operating at an Mtimes higher rate
than the output can replace the input down samplers with successive
delays. This results in Mto1 sample rate reduction without
changing the filter characteristics. The frequency response and
stability of the filter is not disturbed.
In case of interpolation, an up sampler precedes an antiimaging
filter. Using merged delay transformation we are able to arrange the
up samplers after the subfilters in parallel paths with successive
delays. The up samplers and delays are implemented by a commutator
switch model operating at Ltimes faster rate than the input. Output
sampling rate is increased by L and 1toL interpolation is
achieved. The stability and filter characteristics are unchanged.
Filtering and sample rate changes are achieved in the same stage.
This avoids the chain of integrators and differentiators as required
in a variety of cascade integrator comb (CIC) architectures.
Computational costs in terms of number of multiplies per output
sample are compared with polyphase FIR structures and IIR
structures. The cost reduction increases with increasing values of M
or L. For M = 10, the reduction in cost is 82.64% as compared to FIR
decimation filters. As compared to IIR structures, the reduction of
the order of 48% is achieved. In case of interpolation, the cost
reduction is of the order of 45% as compared to polyphase IIR
structures. The reduction in cost is about 68% as compared to
polyphase FIR.
The transformed filters are implemented in Verilog HDL and mapped to
an FPGA of SpartanII technology. Parallel implementation of the
filters provides benefits of parallel processing. Increased
throughput and less hardware requirement are the important
characteristics of this architecture. The technique is expected to
find wide use in multirate signal processing such as efficient
sample rate conversion from CD’s to Digital Audio Tape and Digital
Transmitter/Receivers.

