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Title of Thesis

Efficent Architectural Transformation of Multirate Recursive Filters.

Author(s)

Umar Farooq

Institute/University/Department Details
Department Of Electrical Engineering / University Of Engineering And Technology, Taxila
Session
2008
Subject
Engineering Electrical
Number of Pages
138
Keywords (Extracted from title, table of contents and abstract of thesis)
Multirate, Architectures, Delay, Transformation, Differentiators, Multiplies, Rate, Filters, Successive, Efficent, Recursive, Digital

Abstract
Computationally efficient architectures of multirate recursive filters are presented in this thesis. An analytical transformation is introduced that converts an IIR filter into an efficient decimation/interpolation filter. The transformation is named as merged delay transformation. This transformation is applicable to first order and second order recursive difference equations. The transfer function of the transformed filter is expressed in the form of H(zM) so that noble identity of multirate signal processing may be invoked. An Nth order filter is required to be implemented in parallel using first order and second order sections.In case of decimation, a down sampler follows an anti-aliasing filter. With the help of merged delay transformation, the filter is transformed and arranged to provide
filtering and down sampling in the same stage. This is possible if the filter is implemented in parallel form. Architecture is introduced where down samplers and delays are arranged on the input side. A commutator switch model operating at an M-times higher rate than the output can replace the input down samplers with successive delays. This results in M-to-1 sample rate reduction without changing the filter characteristics. The frequency response and stability of the filter is not disturbed.
In case of interpolation, an up sampler precedes an anti-imaging filter. Using merged delay transformation we are able to arrange the up samplers after the sub-filters in parallel paths with successive delays. The up samplers and delays are implemented by a commutator switch model operating at L-times faster rate than the input. Output sampling rate is increased by L and 1-to-L interpolation is achieved. The stability and filter characteristics are unchanged. Filtering and sample rate changes are achieved in the same stage. This avoids the chain of integrators and differentiators as required in a variety of cascade integrator comb (CIC) architectures.
Computational costs in terms of number of multiplies per output sample are compared with polyphase FIR structures and IIR structures. The cost reduction increases with increasing values of M or L. For M = 10, the reduction in cost is 82.64% as compared to FIR decimation filters. As compared to IIR structures, the reduction of the order of 48% is achieved. In case of interpolation, the cost reduction is of the order of 45% as compared to polyphase IIR structures. The reduction in cost is about 68% as compared to polyphase FIR.
The transformed filters are implemented in Verilog HDL and mapped to an FPGA of Spartan-II technology. Parallel implementation of the filters provides benefits of parallel processing. Increased throughput and less hardware requirement are the important characteristics of this architecture. The technique is expected to find wide use in multirate signal processing such as efficient sample rate conversion from CD’s to Digital Audio Tape and Digital Transmitter/Receivers.

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S. No. Chapter Title of the Chapters Page Size (KB)
1 0 CONTENTS

 

 
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2

1

INTRODUCTION

1.1 Thesis Outline
1.2 References

14
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3 2 MERGED DELAY TRANSFORMATION FOR MULTIRATE SIGNAL PROCESSING

2.1 Introduction
2.2 Merged Delay Transformation
2.3 Transformation of Arbitrary Order IIR Filter
2.4 Matlab Simulations of Merged Delay Transformation
2.5 Conclusions
2.6 References

29
120 KB
4 3 EFFICIENT ARCHITECTURES FOR DECIMATION FILTERS

3.1 Introduction
3.2 Transformation of First Order IIR Filter into an Efficient Decimation Filter
3.3 Frequency Response of Transformed Filters
3.4 Transformation of Second Order IIR Filter into a Decimation Filter
3.5 Frequency Response of Transformed Second Order Filter
3.6 Computational Costs
3.7 Conclusions
3.8 References

49
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5

4

EFFICIENT ARCHITECTURES FOR INTERPOLATION FILTERS

4.1 Introduction
4.2 Transformation of First Order IIR Filter into an Efficient Interpolation Filter
4.3 Transformation of Second Order IIR Filter
4.4 Frequency Response and Pole-Zero Plots of Transformed Filters
4.5 Computational Costs
4.6 Conclusions
4.7 References

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6

5

HARDWARE IMPLEMENTATIONS AND STABILITY ANALYSIS

5.1 Introduction
5.2 Hardware Implementation
5.3 Effect of Merged Delay Transformation on Stability
5.4 Effects of Coefficient Quantization
5.5 Conclusions
5.6 References

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7

6

CONCLUSIONS

6.1 A Comparison of Average Tax Rate and Average Expenditure Rate in Pakistan Sri Lanka and India
6.2 The Analysis of Tax Smoothing for Pakistan
6.3 Concluding Remarks

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7

APPENDIXES

 

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