Logic Decomposition with Technology Mapping for Area & Delay Minimization in FPGA Design

Khalil-ur-Rehman, Dayo (2007) Logic Decomposition with Technology Mapping for Area & Delay Minimization in FPGA Design. Doctoral thesis, Mehran University of Engineering Technology, Jamshoro.

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Abstract

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Item Type: Thesis (Doctoral)
Uncontrolled Keywords: Logic, Decomposition, Technology,Mapping, Area, Delay, Minimization, FPGA, Design
Subjects: T Technology > T Technology (General)
Depositing User: Mr Sami Uddin
Date Deposited: 23 Aug 2017 05:41
Last Modified: 23 Aug 2017 05:41
URI: http://eprints.hec.gov.pk/id/eprint/5536

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