I= FPGA-COMPLIANT MICROPIPELINE BASED ASYNCHRONOUS SYSTEMS
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Title of Thesis
FPGA-COMPLIANT MICROPIPELINE BASED ASYNCHRONOUS SYSTEMS

Author(s)
Yousaf Zafar
Institute/University/Department Details
Mohammad Ali Jinnah University / Faculty Of Engineering And Sciences
Session
2005
Subject
Electronic Engineering
Number of Pages
122
Keywords (Extracted from title, table of contents and abstract of thesis)
synchronous, asynchronous, oscillator, single inverter ring oscillator, pipeline, fpga, micropipeline, risc machine

Abstract
The implementation of a FPGA-compliant micropipline required development or change in fundamental building blocks of standard micropipeline. Therefore, a technology independent and customizable delay element with dynamic calibration capability was developed for FPGAs. Special event controlled register (ECR) for inter-stage latching was also developed that makes use of Muller’s C-element. Unbundled data strategy incorporating bit encoding and return to zero schemes was adopted for FPGA-compliant micropipeline instead of bundled data strategy in full-custom micropipeline. Handshaking protocol also had to be redefined for this novel micropipeline.

The introduced delay element was implemented with a special technology independent circuit called single inverter ring oscillator (SIRO). In order to verify the adaptive nature of SIRO circuit, its behavior as an on-chip oscillator driving co-existing synchronous circuits was also studied. Implementation of externally clock less RISC in FPGA, exhibiting optimal performance without power overhead and electromagnetic compatibility (EMC) is an effort in this direction.

Download Full Thesis
1681.77 KB
S. No. Chapter Title of the Chapters Page Size (KB)
1 0 Contents
134.08 KB
2 1 Introduction 1
89.46 KB
  1.1 Motivation 1
  1.2 Synchronous Vs. Asynchronous Systems 2
  1.3 Reconfigurability 6
  1.4 Contribution: Merger Of Asynchrony And Reconfigurability 7
  1.5 Thesis Layout 8
3 2 Background 10
266.36 KB
  2.1 Asynchrony 10
  2.2 Classification Of Asynchronous Systems 13
  2.3 Evolution Of Asynchrony 23
  2.4 Reconfigurable Mediums 27
4 3 Single Inverter Ring Oscillator 37
174.95 KB
  3.1 SIRO As On-Chip Clock Source 44
  3.2 SIRO Based Delay Element 47
5 4 Instruction Set Architecture 50
60 KB
  4.1 Instruction Set 50
  4.2 Instruction Types 52
  4.3 Pipeline 54
6 5 Externally Clock Less RISC 56
142.25 KB
  5.1 Implementation 56
7 6 FPGA-Compliant Micropipeline 63
196.46 KB
  6.1 SIRO-Based Delay Element 65
  6.2 Unbundled Datapath 67
  6.3 Micropipeline For Fpgas 69
8 7 Reconfigurable Mricropipeline Processor 75
444.46 KB
  7.1 Increment PC Stage 76
  7.2 Fetch Stage 80
  7.3 Decode Stage 80
  7.4 Execute Stage 83
  7.5 Memory Stage 83
  7.6 Reconfigurable Micropipeline Processor 86
  7.7 Edited Implementation In A Xilinx Device 88
9 8 Power Anaysis 95
179.25 KB
  8.1 Factors Affecting Power Calculations 96
10 9 Conclusion And Future Research Plans 104
55.12 KB
  9.1 References 110