FPGA-COMPLIANT MICROPIPELINE BASED ASYNCHRONOUS SYSTEMS

Abstract

The implementation of a FPGA-compliant micropipline required development or change in fundamental building blocks of standard micropipeline. Therefore, a technology independent and customizable delay element with dynamic calibration capability was developed for FPGAs. Special event controlled register (ECR) for inter-stage latching was also developed that makes use of Muller's C-element. Unbundled data strategy incorporating bit encoding and return to zero schemes was adopted for FPGA-compliant micropipeline instead of bundled data strategy in full-custom micropipeline. Handshaking protocol also had to be redefined for this novel micropipeline. The introduced delay element was implemented with a special technology independent circuit called single inverter ring oscillator (SIRO). In order to verify the adaptive nature of SIRO circuit, its behavior as an on-chip oscillator driving co-existing synchronous circuits was also studied. Implementation of externally clock less RISC in FPGA, exhibiting optimal performance without power overhead and electromagnetic compatibility (EMC) is an effort in this direction.