Pakistan Research Repository


Zafar, Yousaf (2005) FPGA-COMPLIANT MICROPIPELINE BASED ASYNCHRONOUS SYSTEMS. PhD thesis, Mohammad Ali Jinnah University, Karachi.



The implementation of a FPGA-compliant micropipline required development or change in fundamental building blocks of standard micropipeline. Therefore, a technology independent and customizable delay element with dynamic calibration capability was developed for FPGAs. Special event controlled register (ECR) for inter-stage latching was also developed that makes use of Muller's C-element. Unbundled data strategy incorporating bit encoding and return to zero schemes was adopted for FPGA-compliant micropipeline instead of bundled data strategy in full-custom micropipeline. Handshaking protocol also had to be redefined for this novel micropipeline. The introduced delay element was implemented with a special technology independent circuit called single inverter ring oscillator (SIRO). In order to verify the adaptive nature of SIRO circuit, its behavior as an on-chip oscillator driving co-existing synchronous circuits was also studied. Implementation of externally clock less RISC in FPGA, exhibiting optimal performance without power overhead and electromagnetic compatibility (EMC) is an effort in this direction.

Item Type:Thesis (PhD)
Uncontrolled Keywords:synchronous, asynchronous, oscillator, single inverter ring oscillator, pipeline, fpga, micropipeline, risc machine
Subjects:Engineering & Technology (e) > Engineering(e1) > Electrical engineering (e1.16)
ID Code:510
Deposited By:Mr. Muhammad Asif
Deposited On:28 Sep 2006
Last Modified:04 Oct 2007 21:01

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