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Title of Thesis

Logic Decomposition with Technology Mapping for Area & Delay Minimization in FPGA Design

Author(s)

Khalil-ur-Rehman Dayo

Institute/University/Department Details
Department of Telecommunication & Control Engineering / Mehran University of Engineering & Technology, Jamshoro
Session
2007
Subject
Telecommunication & Control Engineering
Number of Pages
206
Keywords (Extracted from title, table of contents and abstract of thesis)
Logic, Decomposition, Technology, Mapping, Area, Delay, Minimization, FPGA, Design

Abstract
Available

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13,601 KB
S. No. Chapter Title of the Chapters Page Size (KB)
1 0 CONTENTS

 

v
160 KB
2

1

INTRODUCTION 1
612 KB
3 2 BACKGROUND AND LITERATURE SURVEY 11
2,103 KB
4 3 FIELD PROGRAMMABLE GATES ARRAY'S EXPERIMENTAL ROUTING ARCHITECTURE 42
1,760 KB
5 4 CLUSTER-BASED FPGA ARCHITECTURE AREA AND DAILY ISSUES 71
1,137 KB
6 5 CLUSTER-BASED FPGA ROUTING ARCHITECTURE 90
1,357 KB
7 6 RESULTS AND DISCUSSION 112
618 KB
8 7 CONCLUSION AND FUTURE WORK 123
629 KB
9 8 REFERENCES & APPENDICES 133
4,710 KB