Rehman, Khalil Ur Rehman (2007) Logic Decomposition with Technology Mapping for Area & Delay Minimization in FPGA Design. PhD thesis, Mehran University of Engineering & Technology, Jamshoro.
|Item Type:||Thesis (PhD)|
|Uncontrolled Keywords:||Logic, Decomposition, Technology, Mapping, Area, Delay, Minimization, FPGA, Design|
|Subjects:||Engineering & Technology (e)|
|Deposited By:||Mr. Javed Memon|
|Deposited On:||21 Jul 2010 10:50|
|Last Modified:||13 Jul 2011 12:06|
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