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Title of Thesis  
Error Control Coding with Investigation, Modeling and Designing of Self Checker Circuits for Computer System  
Author(s)  
Mansoor-uz-zafar Dawood  
Institute/University/Department Details  
Mehran University of Eng. & Technology, Jamshoro/Engineering  
Status (Published/ Not Published/ In Press etc)  
Published  
Date of Publishing  
December, 2002  
Subject  
Electronics  
Number of Pages  
361  
   
Keywords (Extracted from title, table of contents and abstract of thesis)  
Error control coding, Self checker circuits, Computer system, Observability, Controllability, Redundancy, Online testing, Offline testing, Linear feedback shift registers (LFSR), Signal isolation circuits, Fault diagnosis, Error detection codes,  

 

 
Abstract  

This thesis examines the fault diagnosis of computer system from the use of existing test techniques to the design and application of self-checking circuits. Initially, some existing techniques for the testing of Computer system (Microprocessor based system) are detailed. Consideration of the testing process at the design stage has resulted in built in test at board and chip level, Common forms of built in test are studied, particularly error detection codes. The aspect of built in test where a system is tested concurrently with normal operation makes extensive use of fault detection and checking circuits. The problem of failures in these checking circuits is resolved with the use of self-checking circuits. The theory of self-checking circuit is introduced' with formal definitions of their characteristics. Based on the tests required to detect all single failures in logic gates and the use of Karnaugh maps, a technique is proposed for the design of self-checking circuits. Circuit designs are presented for several self-checking code checkers. The mechanism required to construct a self-checking microprocessor based system are discussed. These allow a device or circuit failure in a system to be precisely located and include the use of signal isolation circuits. A review of proposals of self-checking devices and system reveals how extensively the various self-checking mechanisms are adopted. Finally, an experimental self-checking computer is described, in which the application of self-checking circuits to the fault diagnosis of microprocessor-based systems is practically evaluated.

 
   
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Sr.No Chapter Table of Contents
 
i 180.kbs
90.KB
1 1

INTRODUCTION

1
287.KB
2 2 BUILT IN TEST, AN INTRODUCTION 7
359.KB
3 3 TECHNIQUES FOR BUILT IN TEST 23
515.KB
4 4 SELF-CHECKING CIRCUITS-AN INTRODUCTION 80
716.KB
5 5 THEORY AND DESIGN SELF CHECKING CIRCUITS 117
338.KB
6 6 FAULT DETECTION AND DIAGNOSIS IN SELF-CHECKING SYSTEMS 187
349.KB
7 7 SELF CHECKING SYSTEMS AND DEVICES: A REVIEW 227
412.KB
8 8 AN EXPERIMENTAL SELF CHECKING COMPUTER 247
133.KB
9 9 SIGNAL ISOLATION CIRCUITS 295
104.KB
10 10 PRACTICAL IN-CIRCUIT EMULATION 312
104.KB
11 11 CONCLUSION AND FURTHER WORK 321
104.KB
12 12 REFERENCES 329
104.KB